This invention relates to solution processed devices and methods for forming such devices.
Semiconducting conjugated polymer thin-film transistors (TFTS) have recently become of interest for applications in cheap, logic circuits integrated on plastic substrates (C. Drury, et al., APL 73, 108 (1998)) and optoelectronic integrated devices and pixel transistor switches in high-resolution active-matrix displays (H. Sirringhaus, et al., Science 280, 1741 (1998), A. Dodabalapur, et al. Appl. Phys. Lett. 73, 142 (1998)). In test device configurations with a polymer semiconductor and inorganic metal electrodes and gate dielectric layers high-performance TFTs have been demonstrated. Charge carrier mobilities up to 0.1 cm2/Vs and ON-OFF current ratios of 106-108 have been reached, which is comparable to the performance of amorphous silicon TFTs (H. Sirringhaus, et al., Advances in Solid State Physics 39, 101 (1999)).
Thin, device-quality films of conjugated polymer semiconductors can be formed by coating a solution of the polymer in an organic solvent onto the substrate. The technology is therefore ideally suited for cheap, large-area solution processing compatible with flexible, plastic substrates. To make full use of the potential cost and ease of processing advantages it is desirable that all components of the devices including the semiconducting layers, the dielectric layers as well as the conducting electrodes and interconnects are deposited from solution.
To fabricate all-polymer TFT devices and circuits the following main problems have to be overcome:
Integrity of multilayer structure: During solution deposition of subsequent semiconducting, insulating and/or conducting layers the underlying layers should not be dissolved, or swelled by the solvent used for the deposition of the subsequent layers. Swelling occurs if solvent is incorporated into the underlying layer which usually results in a degradation of the properties of the layer.
High-resolution patterning of electrodes: The conducting layers need to be patterned to form well-defined interconnects and TFT channels with channel lengths Lxc2x110 xcexcm.
To fabricate TFT circuits vertical interconnect areas (via holes) need to be formed to electrically connect electrodes in different layers of the device.
In WO 99/10939 A2 a method to fabricate an all-polymer TFT is demonstrated that relies on the conversion of the solution-processed layers of the device into an insoluble form prior to the deposition of subsequent layers of the device. This overcomes the problems of dissolution and swelling of underlying layers. However, it severely limits the choice of semiconducting materials, that can be used, to the small and in several respects undesirable class of precursor polymers. Furthermore, cross-linking of the dielectric gate insulating layer makes the fabrication of via-holes through the dielectric layers difficult, such that techniques such as mechanical punching are used (WO 99/10939 A1).
According to one aspect of the present invention there is provided a method for forming on a substrate an electronic device including an electrically conductive or semiconductive material in a plurality of regions, the operation of the device utilising current flow from a first region to a second region, the method comprising: forming a mixture by mixing the material with a liquid; forming on the substrate a confinement structure including a first zone in a first area of the substrate and a second zone in a second area of the substrate, the first zone having a greater repellence for the mixture than the second zone, and a third zone in a third area of the substrate spaced from the second area by the first area, the first zone having a greater repellence for the mixture than the third zone, and depositing the material on the substrate by applying the mixture over the substrate whereby the deposited material may be confined by the relative repellence of the first zone to spaced apart regions defining the said first and second regions of the device and being electrically separated in their plane by means of the relative repellence of the first zone and to be absent from the first area of the substrate so as to resist the flow across the first zone of electrical current between the spaced apart regions of the deposited material.
According to another aspect of the present invention there is provided a method for forming on a substrate an electronic switching device including an electrically conductive or semiconductive material in a plurality of regions, the method comprising: forming a mixture by mixing the material with a liquid; forming on the substrate a confinement structure including a first zone in a first area of the substrate and a second zone in a second area of the substrate, the first zone having a greater repellence for the mixture than the second zone, and a third zone in a third area of the substrate spaced from the first area by the second area, the third zone having a greater repellence for the mixture than the second zone; and depositing the material on the substrate by applying the mixture over the substrate; whereby the deposited material may be confined by the relative repellence of the first and third zones to the said second zone.
The width of the said first area between the second and third areas is suitably less than 20 microns and preferably less than 10 microns. The material formed in the said spaced apart regions suitably forms source and drain electrodes of a transistor.
The method suitably comprises the step of depositing a further material in the space between the said spaced apart regions. The further material deposited in the space between the said spaced apart regions may form a channel of the transistor. The first material may be electrically conductive and the said further material may be semiconductive. The further material may be a polymer material. The further material may be deposited from solution, preferably a solution in a liquid that is not substantially repelled by the first zone.
The width of the said second zone is suitably less than 20 microns. The width of the second zone is suitably less than 10 microns. The material deposited in the second zone is suitably electrically conductive. Such material suitably forms an interconnect. The material may form a gate electrode of a transistor.
The width of the overlap region between the gate electrode of the transistor and the source and drain electrodes, respectively, is preferably less than 20 microns.
The width of the overlap region between the gate electrode of the transistor and the source and drain electrodes, respectively, is preferably less than 10 microns.
The surface of the substrate may be provided by a self-assembled monolayer and at least one of the first and second zones may be defined by patterning of the self-assembled monolayer.
The step of patterning the self-assembled monolayer may be performed by exposure to light through a shadow mask.
The step of patterning the self-assembled monolayer may be performed by bringing the substrate in contact with a soft stamp.
The first and second zones may be formed on the exposed surface of a layer deposited on a planar structural member.
The contact angle of the mixture in the first area is suitably greater by 20 xc2x0, 40xc2x0 or 80xc2x0 than the contact angle of the mixture in the second area.
A method as claimed in any preceding claim, wherein the surface of the substrate is provided by a self-assembled monolayer and at least one of the first and second zones is defined by patterning of the self-assembled monolayer.
The step of patterning the self-assembled monolayer is suitably performed by exposure to light through a shadow mask.
The step of patterning the self-assembled monolayer is performed by bringing the substrate in contact with a soft stamp.
A method as claimed in any preceding claim, wherein the surface of the substrate is provided by a non-polar material and at least one of the first and second zones is defined by surface treatment of the non-polar polymer
The non-polar material may be a polyimide.
The method may comprise the step of mechanically rubbing or otherwise surface treating the polyimide to promote molecular alignment of the polyimide.
The method may comprise the step of optically treating the polyimide to promote molecular alignment of the polyimide.
The said surface treatment may be etching. The said surface treatment may be plasma treatment. The plasma is preferably a carbon tetrafluoride and/or oxygen plasma.
The surface treatment may comprise exposure to ultraviolet light.
Preferably the said one of the zones is the second zone.
The first zone may induce or be capable of inducing an aligned molecular structure of the semiconductive or electrically conductive material.
The first zone is most preferably capable of inducing alignment of polymer chains in the said electrically conductive or semiconductive polymer.
The first zone is suitably capable of inducing alignment of the chains of a polymer material deposited over the first zone.
The said alignment is preferably in a direction running between the second and third zones.
Preferably the, said chains are chains of the said further material.
Preferably the said electrically conductive or semloonductive polymer is deposited by droplet deposition.
Preferably the said electrically conductive or semiconductive polymer is deposited by ink-jet printing.
Preferably the width of at least one of the zones is smaller than the droplet diameter formed in the said inkjet printing step.
Preferably the boundary between the first and second zones is optically distinct, and the method includes the step of optically detecting the boundary between the first and second zones and locating ink-jet printing apparatus relative to the substrate in dependence on that detection.
The first material may be a polymer, preferably a conjugated polymer. The first material may be an Inorganic particulate material capable of suspension In the said liquid.
According to a further aspect of the present invention there is provided a logic circuit, display or memory device formed by the method of any preceding claim.
According to a further aspect of the present invention there is provided a logic circuit, display or memory device comprising an active matrix array of a plurality of transistors formed by the method of any preceding claim.